VLSI Lab / Browser practice
VLSI Practice.
Beginner to Advanced.
Build digital circuits. Write and test Verilog.
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Verilog workspace
Silent recording of the real ECE Lab practice workspace. Build a full adder, run eight checks, inspect five signal waveforms and explore the synthesized gate circuit. The recordings play automatically in sequence.
What you’ll get
Digital Circuits
Build circuits and test their behaviour.
Verilog
Write and synthesize Verilog. Debug with waveforms, then pass the tests to view your synthesized circuit.
VLSI MCQs
Check your fundamentals with topic-wise questions and explanations.
Explore practice
Try for freeDigital Circuits
Boolean Algebra
Logic Gates
Arithmetic Circuits (Gates)
- Half adder, built from gatesTry free →easy
- Full adder, built from gatesmedium
- 1-bit magnitude comparatormedium
- Half subtractor from gatesmedium
- Full subtractor with borrow-inmedium
- 2-bit magnitude comparatormedium
- 2-bit carry-lookahead outputmedium
- Configurable 2-bit adder/subtractormedium
- Compare two unsigned three-bit wordsmedium
- Compare signed two-bit wordsmedium
K-map Minimization
- K-map minimization: reduces to one variableTry free →easy
- K-map minimization: 4-variable reductionmedium
- K-map minimization: 2-variable SOPeasy
- K-map minimization: majority functionmedium
- K-map minimization: when it doesn't simplifyhard
- K-map minimization: using don't-caresmedium
- K-map minimization: Product-of-Sums formmedium
Decoders and Encoders
Code Converters
Parity Generation and Checking
Latches and Flip-Flops
Flip-Flop Conversions
Registers and Counters
- 2-stage SISO registerTry free →medium
- 3-bit SIPO registermedium
- 2-bit PIPO register with load enablemedium
- 3-bit PISO registermedium
- 3-bit universal shift registermedium
- 2-bit synchronous up-countermedium
- Synchronous mod-3 countermedium
- 2-bit enabled up/down countermedium
- 2-bit ripple countermedium
- 3-stage ring countermedium
- 3-stage Johnson countermedium
Verilog
Wires and Basic Gates
Vectors and Operators
Combinational Logic
- Require both permission signalsTry free →easy
- OR gateeasy
- XOR gateeasy
- Choose between two signal sourceseasy
- Half addereasy
- Full addermedium
- Decode a selector into one of four inputsmedium
- 2-to-4 decodermedium
- 2-bit equality comparatormedium
- Resolve competing interrupt requestshard
- Split a byte into two nibbleseasy
- Assemble a byte from two fieldseasy
- Widen a signed sample without changing its valuemedium
- 4-bit subtractoreasy
- 4-bit signed adder with overflow flagmedium
- BCD adderhard
- 8:1 multiplexermedium
- 4-bit binary-to-Gray convertermedium
- 4-bit Gray-to-binary convertermedium
- Append a bit for even paritymedium
- 4-bit even-parity checkermedium
- 2-bit carry-lookahead addermedium
- Signed threshold comparatoreasy
- Shift a byte with signed and unsigned fillmedium
Module Hierarchy
- Build NAND from two supplied blocksTry free →easy
- Link four full adders into a carry chainmedium
- 8:1 multiplexer, built from mux2 instancesmedium
- Wire a helper whose port order is unusualhard
- Connect a helper by declaration ordereasy
- Carry a sample through three registerseasy
- Choose a tap from a register pipelineeasy
- Precompute the upper carry alternativesmedium
- Share an adder between add and subtractmedium
Procedural Blocks
Loops and Generate
Sequential Logic
- Capture a bit at a rising edgeTry free →easy
- D flip-flop with asynchronous resetmedium
- 4-bit register with enablemedium
- T flip-flop (toggle)medium
- 2-bit counter with resetmedium
- Up/down countermedium
- 4-bit shift registermedium
- Sequence detector: two consecutive 1shard
- JK flip-flopeasy
- Gated D-latcheasy
- SR latch (SR flip-flop)easy
- Byte/nibble-enable registermedium
- Decade (BCD) countermedium
- Generic modulo-N countermedium
- 8-bit countereasy
- Bidirectional shift registermedium
- Ring countermedium
- Saturating up-countermedium
- Reload timer / watchdogmedium
- 3-stage Johnson countermedium
- 3-bit PISO registermedium
- 3-bit universal shift registermedium
- One-stage ready/valid registermedium
- Store and read four words on clock edgesmedium
Flip-Flop Conversions
Finite State Machines
- Moore FSM: fixed-cycle traffic lightTry free →easy
- Mealy FSM: rising-edge pulse detectoreasy
- Sequence detector: 101, non-overlappingmedium
- One-hot FSM: coin-operated unlock controllermedium
- FSM from a given state-transition tablemedium
- Multi-signal FSM capstone: request/acknowledge controllerhard
- Rotate priority after each accepted requesthard