Write a module named sr_latch with inputs s, r and output q — the classic Set-Reset latch, often just called an SR flip-flop, the same cross-coupled-gates device you may have seen built in the circuit-building topics, now described in Verilog.
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Wire gates. Test circuit behaviour.
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Write and synthesize Verilog. Inspect waveforms after simulation and the circuit after passing tests.
100 problems
Check your fundamentals. Review explanations.
211 questions
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