Verilog Syntax: Modules, Ports, Types & Operators
VLSI → Verilog & RTL Basics
Verilog Syntax – Modules, Ports, Data Types & Operators
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The module — your hardware unit
module adder #(parameter N = 8) (
input [N-1:0] a, b,
input cin,
output [N-1:0] sum,
output cout
);
assign {cout, sum} = a + b + cin;
endmoduleEverything between
module and endmodule is one hardware block; the parameter list (#(...)) makes it reusable at different widths.Why this works · explanation & key points
Every piece of hardware is described as a module — like a chip, with named ports, internal signals, and behaviour. Modules instantiate other modules to build hierarchy.
Data types
Data type explorer
Continuous connection — like a physical wire. Has no memory; its value is always driven by a combinational expression or a module output.
wire [7:0] data_bus; wire carry_out; assign data_bus = a + b;
Maps to → physical wire / net in the netlist
Why this works · explanation & key points
Choosing the wrong data type is the #1 beginner mistake:
Port directions
Port directions
input wire [7:0] data;
External → Module (read-only inside)
Vectors and bit-selects
wire [7:0] byte; // 8-bit vector, bits 7 down to 0 wire [3:0] nibble; assign nibble = byte[7:4]; // upper nibble (part-select) assign bit3 = byte[3]; // single bit
Why this works · explanation & key points
Vectors are multi-bit signals, declared as [MSB:LSB], sliced with part-selects:
Key operators
| Operator | Symbol | Example | Notes |
|---|---|---|---|
| Bitwise AND | & | a & b | Bit-by-bit AND |
| Bitwise OR | | | a | b | Bit-by-bit OR |
| Bitwise NOT | ~ | ~a | Invert every bit |
| Logical AND | && | (a>0) && (b>0) | Evaluates to 1-bit 0/1 |
| Reduction AND | &a | &byte | ANDs all bits of a vector |
| Concatenation | {,} | {cout,sum} | Joins signals into one |
| Replication | {{}} | {{8{1'b0}}} | Repeats a pattern 8× |
| Ternary | ?: | sel ? a : b | Mux: choose a or b |
Completion saves automatically after you read through to the end.
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