Gowin EDA + Open Yosys/Nextpnr Flow
VLSI → FPGA Bring-up (Tang Nano 9K)
Track the artifact at each tool boundary
Each stage consumes a different representation. Debug the first stage whose output is missing or incorrect.
Synthesize
Yosys translates supported RTL to a technology-mapped netlist for the target FPGA.
RTL → mapped netlistWhere do physical pin assignments matter?
Reveal explanation
In implementation constraints used by the device tools, particularly place and route; RTL port names alone do not select package pins.
Two paths to the same bitstream
The Tang Nano 9K (~₹1300) is unusual for a cheap FPGA board: it's supported by bothits vendor's free proprietary IDE (Gowin EDA) and a fully open-source toolchain. Either one turns your Verilog into a .fsbitstream file the board can actually run — the difference is what happens between "I wrote RTL" and "the chip is configured."
The open chain, stage by stage
.fs bitstream. openFPGALoader flashes that file onto the board over USB.This matters on your resume: it's what actually gets you real silicon to point to for companies like Tessolve and MosChip, who specifically value candidates who've flashed their own RTL onto hardware — not just simulated it.
Try it — walk either chain
Completion saves automatically after you read through to the end.
Next lesson →