AXI4-Lite / APB / AHB
VLSI → Bus Protocols + IP Integration
Three ARM AMBA buses, three jobs
APBis simple, slow, low-power, and register-style (PSEL/PENABLE/PWRITE) — perfect for a UART's control registers, overkill for anything fast. AHB is the older single-master high-performance bus. AXI is the modern standard: 5 independent channels (AW/W/B/AR/R), supports bursts and out-of-order completion. AXI4-Liteis AXI stripped of bursts — the entry point most fresher DV work actually starts with. This is near-universal across companies like Intel, Qualcomm, NVIDIA, AMD, and Samsung India — DV teams strongly expect "AXI" on a fresher resume.
The handshake every AXI channel shares
Every one of AXI's 5 channels uses the same two-signal handshake: the sender asserts VALID when it has real data, the receiver asserts READY when it can accept it, and a transfer only actually happens on a clock edge where both are high. Once VALID is asserted, the AXI spec requires it to stay high (with the same data) until READY arrives — it can never be withdrawn mid-handshake.
Try it — when does a transfer actually happen?
No transfer — waiting
Completion saves automatically after you read through to the end.
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